The present invention provides an improvement over traditional NP domino logic techniques by providing dynamic clock signal timing in order to eliminate short circuit current flow. In the preferred embodiment, the static inverters utilized between logic blocks when implementing traditional NP domino logic circuit design techniques have been eliminated allowing for simpler cascading of the domino building blocks for various logic circuits.
Logic designers utilize various design styles to create logical building blocks which are optimized for a given environment. For example, some logic design styles are directed to preventing race conditions between devices, other design styles take advantage of low power techniques, still other design styles are directed to minimizing power dissipation in a particular circuit.
Power dissipation is a performance measure that refers to the amount of heat energy that is dissipated by a given device during the operation of the device. As a device operates, heat energy is generated. This heat energy is due to the basic operation of the device as gates are switched from state to state, as well because of design defects in the device. If too much heat is built up in the device, the circuit may fail or operate unpredictably. As such, the logic circuit designer must either dissipate the heat energy by means of heat sinks and the like, adding to the cost and overall complexity of the logic circuit design, or minimize its generation or effect in the logic circuit. In terms of efficiency, ideally designers would opt for minimizing the amount of heat energy to be dissipated by eliminating any unnecessary switching, thereby saving on power consumption. This is especially important in portable electronic devices which operate on a finite battery supply. The present invention is directed to a logic design technique which is utilized to minimize power consumption and necessarily the heat energy required to be dissipated by a given circuit by eliminating short circuit current flow in each logic building block.
Heat energy may be created in a logic circuit, inter alia, due to short circuit current flow or glitches. Short circuit current flow will arise if care is not taken as to the sequencing of switching in the device. Specifically, logic circuits which utilize PMOS and NMOS chains often have short circuit current flow as complementary switches transition from state to state. Accordingly, short circuit current power dissipation refers to the amount of power that is dissipated due to short circuit conditions in the logic circuit.
Glitches arise due to race conditions in logic gates, where extra switching occurs due to multi-state transitions during a single clock cycle. Glitch power dissipation refers to the amount of heat energy that is dissipated due to hazard transitions or glitches that arise due to unnecessary switching of the logic devices. In CMOS VLSI circuits, it has been shown that short circuit current can account for as much as 10% of the total power dissipated by a given circuit. Similarly, glitch power dissipation has been shown to be up to 15-20% of the total power dissipated by a CMOS VLSI circuit.
In the prior art, certain design techniques have been utilized to eliminate the need for dissipating glitch power. One such design technique involves the use of a clocked dynamic logic style. In a clocked dynamic logic style, inputs to each gate are switched at most once per clock cycle. In this way, glitch power dissipation is not required by a circuit implementing this technology.
Referring first to FIG. 1, a prior art static logic building block for use in a logic design circuit is shown. The building block 100 is comprised of a PMOS field effect transistor (FET) 102 whose source is tied to a Vcc input, and whose drain is tied to the source of an NMOS FET 104. The drain of the NMOS transistor 104 is coupled to a ground. An input signal 106 is coupled to the gate inputs of both PMOS FET 102 and NMOS FET 104. As such, as the input Vin 106 swings from high to low, the PMOS FET 102 will conduct driving a high signal out on the Vout signal line 108. Conversely, as the V input signal 106 is driven from low to high, the PMOS FET 102 will no longer conduct, while the NMOS FET 104 will begin to conduct thereby driving a ground to the output signal line Vout 108.
As configured, the input swings of Vin and Vout may cause a condition to arise in the FETs 102 and 104, whereby both FET 102 and 104 are on at the same time. In the event that both FET 102 and 104 are on at the same time, a short circuit current flow will arise as the VCC is conducted through the two transistor devices directly to ground. The short circuit current condition arises because the same input signal Vin is used to both turn on and off the complementary FETs 102 and 104. As such, during a transition period between the on and off states, both FETs 102 and 104 will conduct causing a short circuit current to flow.
Referring now to FIG. 2, an example of a prior art glitch free logic technique which implements pre-charge logic is shown. "Pre-charge" logic refers to a logical building block device which has its output pre-charged during one clock cycle (the charge cycle) and thereafter during a second cycle (the evaluation cycle) the status of the input signal to the logic block is evaluated. In this type of circuit technique, the input signal (Vin) is limited to a single transition during the evaluation period.
In this prior art design technique, a building block 200 comprised of a PMOS FET 202 whose source is coupled to VCC and whose drain is coupled to the source of a second PMOS FET 204. The second PMOS FET 204 has its drain coupled to a source input of an NMOS FET 206 whose drain is coupled to ground. In this glitch-free circuit, a first clock signal, Vclk 208 is connected as an input to the gate inputs of PMOS FET 202 and NMOS FET 206. Finally, an input signal Vin 210 is coupled to the gate input of the second PMOS FET 204 whose drain forms the output Vout 212 for this building block circuit 200. This type of circuit utilizes a pre-charge and evaluate clock phase in order to evaluate the status of the input signal Vin.
The clocking diagram is shown in FIG. 2b. For this type of device, the input signal Vin is held at a constant high and, upon a transition from a high to a low state, will drive the output of the building block from a low to a high state. During a charge cycle, the clock line is held high causing PMOS FET 202 to turn off and NMOS FET 206 to turn on. When NMOS FET 206 turns on, a ground is provided on the output signal line Vout 212. As such the building block is "pre-charged" to a logical low output level. During the second portion of the clock cycle, the evaluation cycle, the clock is held low thereby causing the NMOS FET 206 to turn off and the PMOS FET 202 to conduct. When the PMOS FET 202 conducts, the VCC signal is driven to the source input of the PMOS FET 204. As such, if the input signal Vin transitions from a high to low, the second PMOS FET 204 will conduct driving a high VCC output signal on the signal output line Vout 212. Upon the end of the evaluation period, a charge cycle will re-occur causing the output to again be driven to ground.
In this type of dynamic clocked environment, the input signal Vin is only allowed to switch one time during the evaluation phase. As long as this condition is satisfied, then the output signal Vout will transition only a single time during a clock cycle. Those ordinarily skilled in the art will recognize that the reason why the input signal must only be allowed to transition one time during the evaluation phase is because the capacitive nature of the output signal line, Vout 212. In operation, upon transition from a high to a low state on the Vin input signal line, a high output state would result as described above. If the input signal were to transition back to high during the evaluation cycle, the output signal line Vout would remain in the high output state due to the capacitive nature of the output signal line irrespective of the input signal until the capacitive elements in the output signal line were discharged into some load. As such, if the input signal line Vin 210 is allowed to toggle during the evaluation phase, the output signal line Vout 212 will not reflect a true state of the input signal. By requiring a single transition during the evaluation phase, the circuit as shown in FIG. 2a provides for a glitch-free power dissipation because no switching of the devices occur due to race considerations.
However, as can be seen in FIG. 2a, because a single clock signal Vclk 208 is used to drive both the PMOS FET 202 and the NMOS FET 206, a short circuit current condition may arise during the transition phase between the turn on and turn off of FETs 202 and 206. This condition will arise when, at the end of an evaluation period, the input signal remains in the low state causing FET 204 to conduct. During the transition from the end of the evaluation period, FET 202 will turn off while FET 206 begins to turn on. As such, the cascading of the three FETs 202, 204, and 206 will result in a short circuit current during this transition period. While the circuit shown in FIG. 2a provides for a glitch-free logic building block, short circuit current power dissipation still must be compensated for by circuits implementing building blocks as shown in FIG. 2a.
Other dynamic logic techniques including NORA make use of this glitch-free property of dynamic clock circuit timing. Still other designs including Zipper CMOS have been implemented which provide the same basic race or glitch-free environments. However, the majority of the modifications to these basic NP domino techniques have been made to combat charge sharing problems associated with cascading a plurality of building blocks together.